Resistive random-access memory

Resistive random-access memory (RRAM or ReRAM) is a type of non-volatile (NV) random-access (RAM) computer memory that works by changing the resistance across a dielectric solid-state material often referred to as a memristor. This technology bears some similarities to conductive-bridging RAM (CBRAM), and phase-change memory (PCM).

CBRAM involves one electrode providing ions that dissolve readily in an electrolyte material, while PCM involves generating sufficient Joule heating to effect amorphous-to-crystalline or crystalline-to-amorphous phase changes. On the other hand, RRAM involves generating defects in a thin oxide layer, known as oxygen vacancies (oxide bond locations where the oxygen has been removed), which can subsequently charge and drift under an electric field. The motion of oxygen ions and vacancies in the oxide would be analogous to the motion of electrons and holes in a semiconductor.

RRAM is currently under development by a number of companies, some of which have filed patent applications claiming various implementations of this technology.[1][2][3][4][5][6][7] RRAM has entered commercialization on an initially limited KB-capacity scale.[8]

Although commonly anticipated as a replacement technology for flash memory, the cost benefit and performance benefit of RRAM have not been obvious enough to most companies to proceed with the replacement. A broad range of materials apparently can potentially be used for RRAM. However, the recent discovery[9] that the popular high-κ gate dielectric HfO2 can be used as a low-voltage RRAM has greatly encouraged others to investigate other possibilities. Even more recently SiOx has been identified to offer significant benefits. Weebit-Nano Ltd is one company that is pursuing SiOx and has already demonstrated functional devices.

History

In February 2012 Rambus bought an RRAM company called Unity Semiconductor for $35 million.[10] Panasonic launched an RRAM evaluation kit in May 2012, based on a tantalum oxide 1T1R (1 transistor – 1 resistor) memory cell architecture.[11]

In 2013, Crossbar introduced an RRAM prototype as a chip about the size of a postage stamp that could store 1 TB of data. In August 2013, the company claimed that large-scale production of their RRAM chips was scheduled for 2015.[12] The memory structure (Ag/a-Si/Si) closely resembles a silver-based CBRAM.

Different forms of RRAM have been disclosed, based on different dielectric materials, spanning from perovskites to transition metal oxides to chalcogenides. Silicon dioxide was shown to exhibit resistive switching as early as 1967,[13] and has recently been revisited.[14][15]

Leon Chua argued that all two-terminal non-volatile memory devices including RRAM should be considered memristors.[16] Stan Williams of HP Labs also argued that RRAM was a memristor.[17] However, others challenged this terminology and the applicability of memristor theory to any physically realizable device is open to question.[18][19] Whether redox-based resistively switching elements (RRAM) are covered by the current memristor theory is disputed.[20]

In 2014 researchers announced a device that used a porous silicon oxide dielectric with no edge structure. In 2010 conductive filament pathways were discovered, leading to the later advance. It can be manufactured at room temperature and has a sub-2V forming voltage, higher on-off ratio, lower power consumption, nine-bit capacity per cell, higher switching speeds and improved endurance.[21]

Forming

Filament forming: A 50 nm × 50 nm RRAM cell by Crossbar shows the instance of filament forming when the current abruptly increases beyond a certain voltage. A transistor is often used to limit current to prevent a runaway breakdown following the filament formation.

The basic idea is that a dielectric, which is normally insulating, can be made to conduct through a filament or conduction path formed after application of a sufficiently high voltage. The conduction path can arise from different mechanisms, including vacancy or metal defect migration. Once the filament is formed, it may be reset (broken, resulting in high resistance) or set (re-formed, resulting in lower resistance) by another voltage. Many current paths, rather than a single filament, are possibly involved.[22]

The low-resistance path can be either localized (filamentary) or homogeneous. Both effects can occur either throughout the entire distance between the electrodes or only in proximity to one of the electrodes. Filamentary and homogenous switching effects can be distinguished by measuring the area dependence of the low-resistance state.[23]

Under certain conditions, the forming operation may be bypassed.[24] It is expected that under these conditions, the initial current is already quite high compared to insulating oxide layers.

CBRAM cells generally would not require forming if Cu ions are already present in the electrolyte, having already been driven-in by a designed photo-diffusion or annealing process; such cells may also readily return to their initial state.[25] In the absence of such Cu initially being in the electrolyte, the voltage would still be applied directly to the electrolyte, and forming would be a strong possibility.[26]

Operation styles

For random-access type memories, a 1T1R (one transistor, one resistor) architecture is preferred because the transistor isolates current to cells that are selected from cells that are not. On the other hand, a cross-point architecture is more compact and may enable vertically stacking memory layers, ideally suited for mass-storage devices. However, in the absence of any transistors, isolation must be provided by a "selector" device, such as a diode, in series with the memory element or by the memory element itself. Such isolation capabilities are inferior to the use of transistors if the on/off ratio for the selector is not sufficient, limiting the ability to operate very large arrays in this architecture. Thin film based threshold switch can work as a selector for bipolar and unipolar RRAM. Threshold switch-based selector was demonstrated for 64 Mb array.[27] However, One shouldn't forget that the cross-point architecture requires BEOL compatible two terminal selectors like punch-through diode for bipolar RRAM[28] or PIN diode for unipolar RRAM.[29]

Polarity can be either binary or unary. Bipolar effects cause polarity to reverse when switching from low to high resistance (reset operation) compared to switching high to low (set operation). Unipolar switching leaves polarity unaffected, but uses different voltages.

Material systems for resistive memory cells

Multiple inorganic and organic material systems display thermal or ionic resistive switching effects. These can be grouped into the following categories:[23]

Demonstrations

Papers at the IEDM Conference in 2007 suggested for the first time that RRAM exhibits lower programming currents than PRAM or MRAM without sacrificing programming performance, retention or endurance.[30] On 30 April 2008, HP announced that they had discovered the memristor, originally envisioned as a missing 4th fundamental circuit element by Chua in 1971. On 8 July they announced they would begin prototyping RRAM using their memristors.[31] At IEDM 2008, the highest-performance RRAM technology to date was demonstrated by ITRI, showing switching times less than 10 ns and currents less than 30 mA. At IEDM 2010, ITRI again broke the speed record, showing <0.3 ns switching time, while also showing process and operation improvements to allow yield up to 100%.[32] IMEC presented updates of their RRAM program at the 2012 Symposia on VLSI Technology and Circuits, including a solution with a 500 nA operating current.[33]

Future applications

Compared to PRAM, RRAM operates at a faster timescale (switching time can be less than 10 ns), while compared to MRAM, it has a simpler, smaller cell structure (less than 8F² MIM stack). A vertical 1D1R (one diode, one resistive switching device) integration can be used for crossbar memory structure to reduce the unit cell size to 4F² (F is the feature dimension).[34] Compared to flash memory and racetrack memory, a lower voltage is sufficient, and hence it can be used in low-power applications. Also, due to its relatively small access latency and high density, RRAM is considered a promising candidate for designing caches.[35]

ITRI has shown that RRAM is scalable below 30 nm.[36] The motion of oxygen atoms is a key phenomenon for oxide-based RRAM;[37] one study indicated that oxygen motion may take place in regions as small as 2 nm.[38] It is believed that if a filament is responsible, it would not exhibit direct scaling with cell size.[39] Instead, the current compliance limit (set by an outside resistor, for example) could define the current-carrying capacity of the filament.[40]

A significant hurdle to realizing the potential of RRAM is the sneak path problem that occurs in larger passive arrays. In 2010, complementary resistive switching (CRS) was introduced as a possible solution to sneak-path current interference.[41] In the CRS approach, the information storing states are pairs of high- and low-resistance states (HRS/LRS and LRS/HRS) so that the overall resistance is always high, allowing larger passive crossbar arrays.

A drawback to the initial CRS solution is the requirement for switching endurance caused by conventional destructive readout based on current measurements. A new approach for a nondestructive readout based on capacity measurement potentially lowers the requirements for both material endurance and power consumption.[42] Bi-layer structure is used to produce the nonlinearity in LRS to avoid the sneak path problem.[43] A single-layer device exhibiting a strong nonlinear conduction in LRS was reported.[44] Another bi-layer structure was introduced for bipolar RRAM to improve the HRS and stability.[45]

Another solution to the sneak current issue is to perform read and reset operations in parallel across an entire row of cells, while using set on selected cells.[46] In this case, for a 3D-RRAM 1TNR array, with a column of N RRAM cells situated above a select transistor, only the intrinsic nonlinearity of the HRS is required to be sufficiently large, since the number of vertical levels N is limited (e.g., N = 8–32), and this has been shown possible for a low-current RRAM system.[47]

Modeling of 2D and 3D caches designed with RRAM and other non-volatile random access memories such as MRAM and PCM can be done using DESTINY[48] tool.

References

  1. ↑ U.S. Patent 6,531,371
  2. ↑ U.S. Patent 7,292,469
  3. ↑ U.S. Patent 6,867,996
  4. ↑ U.S. Patent 7,157,750
  5. ↑ U.S. Patent 7,067,865
  6. ↑ U.S. Patent 6,946,702
  7. ↑ U.S. Patent 6,870,755
  8. ↑ "MN101L ReRAM Embedded MCUs - Panasonic | Mouser". www.mouser.com. Retrieved 2016-06-08.
  9. ↑ H-Y. Lee et al., IEDM 2008.
  10. ↑ Mellor, Chris (7 February 2012), Rambus drops $35m for Unity Semiconductor
  11. ↑ "the new microcontrollers with on-chip non-volatile memory ReRAM" (Press release). Panasonic. May 15, 2012. Retrieved May 16, 2012.
  12. ↑ "Next-gen storage wars: In the battle of RRAM vs 3D NAND flash, all of us are winners" (Press release). PC World. August 9, 2013. Retrieved January 28, 2014.
  13. ↑ Lamb, D R; Rundle, P C (1967). "A non-filamentary switching action in thermally grown silicon dioxide films". British Journal of Applied Physics. 18: 29. Bibcode:1967BJAP...18...29L. doi:10.1088/0508-3443/18/1/306.
  14. ↑ Park, In-Sung; Kim, Kyong-Rae; Lee, Sangsul; Ahn, Jinho (2007). "Resistance Switching Characteristics for Nonvolatile Memory Operation of Binary Metal Oxides". Japanese Journal of Applied Physics. 46 (4B): 2172. Bibcode:2007JaJAP..46.2172P. doi:10.1143/JJAP.46.2172.
  15. ↑ Mehonic, A.; Cueff, S. B.; Wojdak, M.; Hudziak, S.; Jambois, O.; Labbé, C.; Garrido, B.; Rizk, R.; Kenyon, A. J. (2012). "Resistive switching in silicon suboxide films". Journal of Applied Physics. 111 (7): 074507. Bibcode:2012JAP...111g4507M. doi:10.1063/1.3701581.
  16. ↑ Chua, L. O. (2011), "Resistance switching memories are memristors", Applied Physics A, 102 (4): 765–783, Bibcode:2011ApPhA.102..765C, doi:10.1007/s00339-011-6264-9
  17. ↑ Mellor, Chris (10 October 2011), "HP and Hynix to produce the memristor goods by 2013", The Register, retrieved 2012-03-07
  18. ↑ Meuffels, P.; Soni, R. (2012), "Fundamental Issues and Problems in the Realization of Memristors", arXiv:1207.7319Freely accessible
  19. ↑ Di Ventra, Massimiliano; Pershin, Yuriy V. (2013). "On the physical properties of memristive, memcapacitive and meminductive systems". Nanotechnology. 24 (25): 255201. arXiv:1302.7063Freely accessible. Bibcode:2013Nanot..24y5201D. doi:10.1088/0957-4484/24/25/255201. PMID 23708238.
  20. ↑ Valov, I.; Linn, E.; Tappertzhofen, S.; Schmelzer, S.; van den Hurk, J.; Lentz, F.; Waser, R. (2013). "Nanobatteries in redox-based resistive switches require extension of memristor theory". Nature Communications. 4: 1771. Bibcode:2013NatCo...4E1771V. doi:10.1038/ncomms2784. PMC 3644102Freely accessible. PMID 23612312.
  21. ↑ "the Foresight Institute » Blog Archive » Nanotechnology-based next generation memory nears mass production". Foresight.org. Retrieved 2014-08-13.
  22. ↑ Lee, D.; Seong, D. J.; Jo, I.; Xiang, F.; Dong, R.; Oh, S.; Hwang, H. (2007). "Resistance switching of copper doped MoO[sub x] films for nonvolatile memory applications". Applied Physics Letters. 90 (12): 122104. Bibcode:2007ApPhL..90l2104L. doi:10.1063/1.2715002.
  23. 1 2 "Advanced Engineering Materials – Wiley Online Library". Aem-journal.com. Retrieved 2014-08-13.
  24. ↑ Y. S. Chen et al., Forming-free HfO2 Bipolar RRAM Device with Improved Endurance and High Speed Operation, VLSI-TSA 2009, p. 37. http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=5159281
  25. ↑ M.Balakrishnan et al., A Low Power Non-Volatile Memory Element Based on Copper in Deposited Silicon Oxide, NVMTS 2006, http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4228446
  26. ↑ S. Sills et al., A Copper ReRAM Cell for Storage Class Memory Applications, Proc. Symp. VLSI Tech. 2014, p. 64.
  27. ↑ I.V. Karpov, D. Kencke, D. Kau, S. Tang and G. Spadini, MRS Proceedings, Volume 1250, 2010
  28. ↑ V. S. S. Srinivasan et al., Punchthrough-Diode-Based Bipolar RRAM Selector by Si Epitaxy," Electron Device Letters, IEEE , vol.33, no.10, pp.1396,1398, Oct. 2012 doi: 10.1109/LED.2012.2209394
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  30. ↑ Tsunoda, K.; Kinoshita, K.; Noshiro, H.; Yamazaki, Y.; Iizuka, T.; Ito, Y.; Takahashi, A.; Okano, A.; Sato, Y.; Fukano, T.; Aoki, M.; Sugiyama, Y. (2007). "Low Power and High Speed Switching of Ti-doped NiO ReRAM under the Unipolar Voltage Source of less than 3 V". 2007 IEEE International Electron Devices Meeting. p. 767. doi:10.1109/IEDM.2007.4419060. ISBN 978-1-4244-1507-6.
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  32. ↑ H-Y. Lee et al., IEDM 2010.
  33. ↑ L. Goux et al., 2012 Symp. on VLSI Tech. Dig. of Tech. Papers, 159 (2012).
  34. ↑ Zhang, Yang; Duan, Ziqing; Li, Rui; Ku, Chieh-Jen; Reyes, Pavel I; Ashrafi, Almamun; Zhong, Jian; Lu, Yicheng (2013). "Vertically integrated ZnO-Based 1D1R structure for resistive switching". Journal of Physics D: Applied Physics. 46 (14): 145101. Bibcode:2013JPhD...46n5101Z. doi:10.1088/0022-3727/46/14/145101.
  35. ↑ "A Survey Of Architectural Approaches for Managing Embedded DRAM and Non-volatile On-chip Caches", Mittal et al., TPDS, 2015.
  36. ↑ Y.-S. Chen et al., IEDM 2009.
  37. ↑ New Non-Volatile Memory Workshop 2008, Hsinchu, Taiwan.
  38. ↑ Cen, C.; Thiel, S.; Hammerl, G.; Schneider, C. W.; Andersen, K. E.; Hellberg, C. S.; Mannhart, J.; Levy, J. (2008). "Nanoscale control of an interfacial metal–insulator transition at room temperature". Nature Materials. 7 (4): 298. Bibcode:2008NatMa...7..298C. doi:10.1038/nmat2136. PMID 18311143.
  39. ↑ I. G. Baek et al.,IEDM 2004.
  40. ↑ Lin, Chih-Yang; Wu, Chen-Yu; Wu, Chung-Yi; Hu, Chenming; Tseng, Tseung-Yuen (2007). "Bistable Resistive Switching in Al2O3 Memory Thin Films". Journal of the Electrochemical Society. 154 (9): G189. doi:10.1149/1.2750450.
  41. ↑ Linn, Eike; Rosezin, Roland; Kügeler, Carsten; Waser, Rainer (2010). "Complementary resistive switches for passive nanocrossbar memories". Nature Materials. 9 (5): 403. Bibcode:2010NatMa...9..403L. doi:10.1038/nmat2748. PMID 20400954.
  42. ↑ Tappertzhofen, S; Linn, E; Nielen, L; Rosezin, R; Lentz, F; Bruchhaus, R; Valov, I; Böttger, U; Waser, R (2011). "Capacity based nondestructive readout for complementary resistive switches". Nanotechnology. 22 (39): 395203. Bibcode:2011Nanot..22M5203T. doi:10.1088/0957-4484/22/39/395203. PMID 21891857.
  43. ↑ Joshua Yang, J.; Zhang, M.-X.; Pickett, Matthew D.; Miao, Feng; Paul Strachan, John; Li, Wen-Di; Yi, Wei; Ohlberg, Douglas A. A.; Joon Choi, Byung; Wu, Wei; Nickel, Janice H.; Medeiros-Ribeiro, Gilberto; Stanley Williams, R. (2012). "Engineering nonlinearity into memristors for passive crossbar applications". Applied Physics Letters. 100 (11): 113501. Bibcode:2012ApPhL.100k3501J. doi:10.1063/1.3693392.
  44. ↑ Mehonic, Adnan; Cueff, Sébastien; Wojdak, Maciej; Hudziak, Stephen; Labbé, Christophe; Rizk, Richard; Kenyon, Anthony J (2012). "Electrically tailored resistance switching in silicon oxide". Nanotechnology. 23 (45): 455201. Bibcode:2012Nanot..23S5201M. doi:10.1088/0957-4484/23/45/455201. PMID 23064085.
  45. ↑ Zhang, Yang; Duan, Ziqing; Li, Rui; Ku, Chieh-Jen; Reyes, Pavel; Ashrafi, Almamun; Lu, Yicheng (2012). "FeZnO-Based Resistive Switching Devices". Journal of Electronic Materials. 41 (10): 2880. Bibcode:2012JEMat..41.2880Z. doi:10.1007/s11664-012-2045-2.
  46. ↑ H. S. Yoon et al., Vertical cross-point resistance change memory for ultra-high density non-volatile memory applications, Proc. Symp. VLSI Tech. 2009, pp. 26–27. http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=5200621&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D5200621
  47. ↑ F. T. Chen et al., Write Scheme Allowing Reduced LRS Nonlinearity Requirement in a 3D-RRAM Array With Selector-Less 1TNR Architecture, IEEE Elec. Dev. Lett. vol. 35, 223 (2014). http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6701133
  48. ↑ Poremba et al., "DESTINY: A Tool for Modeling Emerging 3D NVM and eDRAM caches", DATE, 2015.
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