Elmore delay

Elmore delay^[1] is a simple approximation to the delay through an RC network in an electronic system. It is often used in applications such as logic synthesis, delay calculation, static timing analysis, placement and routing, since it is simple to compute (especially in tree structured networks, which are the vast majority of signal nets within ICs) and is reasonably accurate. Even where it is not accurate, it is usually faithful, in the sense that reducing the Elmore delay will almost always reduce the true delay, so it is still useful in optimization.

Elmore delay can be thought of in several ways, all mathematically identical.

• For tree structured networks, find the delay through each segment as the R (electrical resistance) times the downstream C (electrical capacitance). Sum the delays from the root to the sink.
• Assume the output is a simple exponential, and find the exponential that has the same integral as the true response. This is also equivalent to moment matching with one moment, since the first moment is a pure exponential.
• Find a one pole approximation to the true frequency response. This is a first-order Padé approximation.

There are many extensions to Elmore delay. It can be extended to upper and lower bounds,^[2] to include inductance as well as R and C, to be more accurate (higher order approximations)^[3] and so on. See delay calculation for more details and references.

See also

• Delay calculation
• Static timing analysis

References